![]() Key to this gate circuit’s elegant design is the complementary use of both P- and N-channel IGFETs. Note that the output of this gate never floats as is the case with the simplest TTL circuit: it has a natural “totem-pole” configuration, capable of both sourcing and sinking load current. ![]() Using field-effect transistors instead of bipolar transistors has greatly simplified the design of the inverter gate. Complementary Metal Oxide Semiconductors (CMOS) Clearly, this circuit exhibits the behavior of an inverter, or NOT gate. Thus, the output of this gate circuit is now “low” (0). The upper transistor, having zero voltage applied between its gate and substrate, is in its normal mode: off. Now the lower transistor (N-channel) is saturated because it has sufficient voltage of the correct polarity applied between gate and substrate (channel) to turn it on (positive on gate, negative on the channel). Next, we’ll move the input switch to its other position and see what happens: This makes the output “high” (1) for the “low” (0) state of the input. Thus, the action of these two transistors are such that the output terminal of the gate circuit has a solid connection to V dd and a very high resistance connection to ground. The lower transistor, having zero voltage between gate and substrate (source), is in its normal mode: off. So, in the above illustration, the top transistor is turned on. When the channel (substrate) is made more positive than the gate (gate negative in reference to the substrate), the channel is enhanced and current is allowed between source and drain. The upper transistor is a P-channel IGFET. It takes an applied voltage between gate and drain (actually, between gate and substrate) of the correct polarity to bias them on. Please note that these IGFET transistors are E-type (Enhancement-mode), and so are normally-off devices. Let’s connect this gate circuit to a power source and input switch, and examine its operation. This label follows the same convention as “V cc” in TTL circuits: it stands for the constant voltage applied to the drain of a field effect transistor, in reference to ground.įield Effect Transistors in Gate Circuits Notice the “V dd” label on the positive power supply terminal. Take for instance, the following inverter circuit built using P- and N-channel IGFETs: Being voltage-controlled rather than current-controlled devices, IGFETs tend to allow very simple circuit designs. Field-Effect Transistorsįield-effect transistors, particularly the insulated-gate variety, may be used in the design of gate circuits. This, however, is not the only way we can build logic gates. Up until this point, our analysis of transistor logic circuits has been limited to the TTL design paradigm, whereby bipolar transistors are used, and the general strategy of floating inputs being equivalent to “high” (connected to V cc) inputs-and correspondingly, the allowance of “open-collector” output stages-is maintained.
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